1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device with an Insulated-Gate Field-Effect Transistor (IGFET) using selective epitaxial growth of silicon (Si).
2. Description of the Prior Art
In recent years, semiconductor devices have been becoming miniaturized more and more according to the increase in their integration scale. Under such the circumstances, a lot of electronic devices such as memory or logic devices have been integrated on a semiconductor substrate or chip. In these highly-integrated semiconductor devices, IGFETs such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are typically used.
To cope with the progressing miniaturization and increasing integration tendency, there has been the need to solve the problems induced by the short-channel effects in IGFETs. A known solution to solve the problems is to decrease the depth of source/drain regions of the IGFETs. However, the depth decrease of the source/drain regions causes another problem that the sheet resistance of the source/drain regions is increased and simultaneously, the contact resistance of the source/drain regions with wiring materials is also increased.
To solve this problem, there has been developed several methods that epitaxial layers are respectively formed on the source/drain regions by the use of the selective epitaxial growth technique. An example of the conventional methods of this sort is shown in FIGS. 1A to 1C.
It is needless to say that a lot of IGFETs are formed on a semiconductor substrate. However, only one of the IGFETs is explained here for the sake of simplification.
First, a basic transistor configuration is formed through the popular processes, as shown in FIG. 1A.
Specifically, an isolation dielectric 102 is selectively formed on a main surface of a single-crystal Si substrate 101, thereby defining an active region 101A where an IGFET 120 is formed. A gate oxide 103 is formed on the surface of the substrate 101 in the active region 101A. A polycrystalline Si (poly-Si) gate electrode 104 is formed on the gate oxide 103. Source/drain regions 106a and 106b are formed in the surface area of the substrate 101 at each side of the gate electrode 104 in the active region 101A. Dielectric sidewalls 105a and 105b are respectively formed on the source/drain regions 106a and 106b at each side of the gate electrode 104. The sidewalls 105a and 105b are in contact with the corresponding side faces of the gate electrode 104.
Next, by the use of the selective epitaxial growth technique, single-crystal Si epitaxial layers 108a and 108b are respectively formed on the uncovered source/drain regions 106a and 106b and at the same time, a poly-Si layer 108c is formed on the uncovered gate electrode 104, as shown in FIG. 1B. This epitaxial growth process of Si is carried out in self-alignment to the isolation dielectric 102 and the sidewall oxides 105.
Subsequently, a refractory metal such as titanium (Ti) is deposited to cover the whole surface of the substrate 101, thereby forming a refractory metal layer (not shown) in contact with the single-crystal Si epitaxial layers 108a and 108b and the poly-Si layer 108c. Then, the substrate 101 equipped with the refractory metal layer is annealed by heat treatment to cause a silicidation reaction between the refractory metal layer and the single-crystal Si epitaxial layers 108a and 108b and the poly-Si layer 108c.
Thus, refractory silicide layers 111a and 111b are formed on the source/drain regions 106a and 106b, respectively. At the same time as this, a refractory silicide layer 111c is formed on the gate electrode 104. The state at this stage is shown in FIG. 1C.
Through the above-described processes, the IGFET 120 is constituted by the gate oxide 103, the gate electrode 104, the source/drain regions 106a and 106b, the dielectric sidewalls 105a and 105b, the single-crystal Si epitaxial layers 111a and 111b, and the poly-Si layer 111c, as shown in FIG. 1C.
The single-crystal Si epitaxial layers 111a and 111b have the same functions as those of the source/drain regions 106a and 106b, respectively. The poly-Si layer 111c has the same function as that of the gate electrode 104.
With the conventional fabrication method of a semiconductor device shown in FIGS. 1A to 1C, the above-identified problem that the sheet resistance of the source/drain regions 106a and 106b is increased and the contact resistance of the source/drain regions 106a and 106b with wiring materials is increased is able to be solved while the source/drain regions 106a and 106b are formed shallow.
However, in the selective epitaxial growth process of Si shown in FIG. 1B, there is a possibility that poly-Si or amorphous Si is deposited on the surfaces of the dielectric sidewalls 105a and 105b and the isolation dielectric 102. This is caused by lowering of the degree of selectivity due to deviation in epitaxial growth condition.
In FIG. 1B, the reference symbol 118 denotes grains of poly-Si or amorphous Si deposited on the surfaces of the dielectric sidewalls 105a and 105b. In FIG. 1C, the reference symbol 121 denotes the grains of refractory silicide produced due to the silicidation reaction of the poly-Si or amorphous Si grains 118.
The conductive refractory silicide grains 121 cause a problem that electrical short-circuit tends to occur between the gate electrode 104 and any one of the source/drain regions 106a and 106b. This electrical short-circuit leads to leakage currents of the IGFET 120.
As the single-crystal Si epitaxial layers 108a and 108b, and the poly-Si layer 108c become thicker, the substantial distances between the gate electrode 104 and the single-crystal Si epitaxial layers 108a and 108b formed on the source/drain regions 106a and 106b become shorter. In this case, therefore, the electrical short-circuit tends to occur even if the refractory silicide grains 121 have a smaller size.
Additionally, the Japanese Non-Examined Patent Publication No. 63-166271 published in 1988 discloses another fabrication method of a semiconductor device with an IGFET.
In this method, prior to a wet etching process for selectively removing a silicon dioxide (SiO.sub.2) layer formed on a main surface of a single-crystal Si substrate to result in a gate oxide, silicon nitride (Si.sub.3 N.sub.4) layers are deposited on the surfaces of dielectric sidewalls made of SiO.sub.2. Because Si.sub.3 N.sub.4 has a lower etch rate than SiO.sub.2 against a popular etchant such as hydrogen fluoride (HF), the dielectric sidewalls are prevented from being etched during this wet etching process.
Accordingly, the electrical short-circuit between a gate electrode and source/drain regions due to etching of the dielectric sidewalls at their bottoms during the above wet etching process is prevented from occurring.
As clearly seen, the conventional fabrication method disclosed in the Japanese Non-Examined Patent Publication No. 63-166271 is unable to solve the previously-explained problem of electrical short-circuit due to the grains 121 of refractory silicide.